1. Field of the Invention
The present invention relates to memory deices and method(s) for fabricating a semiconductor (memory) device, and more particularly, to a cylindrical capacitor and/or a one cylinder storage (OCS) device and method(s) for making the same using a side lobe phenomenon.
2. Discussion of the Related Art
A dynamic random access memory (DRAM) is one of many typical memory devices. In one widely-known embodiment, the DRAM has a unit cell including one transistor and one capacitor. In comparison to the transistor, the capacitor is generally relatively large. In this respect to improve integration of the DRAM, efforts to decrease the size of the capacitor while maintaining a storage capacity of the capacitor have been made.
DRAM is typically used to obtain higher integration than is generally available with Static random access memory (SRAM). A DRAM cell generally includes a Field Effect Transistor (FET) and a capacitor for storing a bit of bin data. As shown in FIG. 1, for example, DRAM cell 100 may include transistor 1 and capacitor 4. Transistor 1 is coupled to bit line 2 at the source terminal and to word line 3 at the gate terminal of the transistor. The drain terminal of transistor 1 is coupled to storage electrode 5 (otherwise referred to as the “lower electrode”) of capacitor 4. A dielectric material 6 is arranged between lower electrode 5 and plate electrode 7 (otherwise referred to as the “upper electrode”) for storing a charge therein.
The performance characteristic of a DRAM cell are closely related to the capacitance of the memory cell capacitor. For example, the low voltage characteristics and soft error characteristics of the memory cell are improved as the capacitance of the memory cell capacitor increases. However, as semiconductor memory devices become more highly-integrated, the horizontal area available to the cell capacitor shrink. This tends to decrease capacitance by limiting the surface area of the capacitor electrodes. Thus, methods are needed for increasing the capacitance of the memory cell capacitor, while maintaining high cell integration and reliable operation.
A number of techniques have been suggested for increasing the capacitance of a memory cell capacitor, while maintaining high memory cell integrating. Such methods include using a thin film to form the capacitor dielectric layer, using a material with a high dielectric constant for the dielectric layer, and increasing the effective area of a capacitor electrode by making a cylinder-type capacitor and/or by growing hemispherical sizing (HSGs) on the surface of the capacitor electrode. The current discussion focuses on various methods for forming a cylinder-type capacitor, which functions to increase cell capacitance by increasing the electrode surface area in a vertical, rather than horizontal, direction.
The storage capacity of the capacitor can be calculated by ‘C=ε×A/d’, wherein ‘C’ is a capacitor storage ability, ‘A’ is an area of an electrode, and ‘d’ is a distance between two electrodes. That is, the storage capacity is in proportion to a dielectric constant ε of a dielectric substance, and the area of the electrode for covering the dielectric substance. Also, the storage capacity is in inverse proportion to the distance between the two electrodes
Accordingly, methods for improving the capacitor storage ability may focus on improving the dielectric properties of the dielectric substance and modifying a geometrical shape of the capacitor. In one method for modifying the geometrical shape of The capacitor, the capacitor may have a cylindrical shape. In this case, if the capacitor has a cylindrical shape, it is possible to increase the surface area of the electrode in the capacitor, thereby decreasing the effective unit area of the capacitor.
However, forming a cylindrical capacitor may result in various problems in the fabrication process. For example, in one typical fabrication process for a cylindrical capacitor, it is impossible to obtain a cylindrical shape in the capacitor with one mask during the photo process. As a result it may require several process steps for fabricating the cylindrical shape of the capacitor, thereby complicating the fabrication process. Also, the aforementioned fabrication process may include a wet etch process, which may damage the wafer. Accordingly, there is a need to develop a new fabrication process that can overcome the aforementioned problems in decreasing the size of the capacitor.
A method for fabricating a related art capacitor will be described as follows.
FIGS. 2A to 2H are cross sectional views of a process for fabricating a cylindrical capacitor according to the related art.
As shown in FIG. 2A, an insulating interlayer 20 (which may contain one or form insulator layers, such as USG, FSG, TEOS and/or silicon nitride, such as a USG/FSG/TEOS/USG stack) is formed on a semiconductor substrate 10, and a nitride layer 30 is deposited on the insulating interlayer 20. Then, the nitride layer 30 is pattered to form a bottom plate opening, then used as an etch stop or mask for the following process. That is, the nitride layer 30 remains on a portion of the substrate that dots not form the cylindrical capacitor. Then, a predetermined portion of the insulating interlayer 20 is removed by photolithography, thereby forming a contact hole 21. Then, a conductive layer, for example, a first polysilicon layer 40 is deposited on the insulating interlayer 20, to completely fill to contact hole 21.
As shown in FIG. 2B, a silicon oxide layer 50 (e.g., silicon dioxide, such as USG or TEOS) is deposited on the first polysilicon layer 40, to form an area corresponding to an inner part of a subsequently formed lower electrode having a cylindrical shape.
Referring to FIG. 2C, a photoresist layer is deposited on the silicon oxide layer 50, and then an expose and development process is performed thereon, thereby forming a photoresist pattern 60, defining a capacitor area.
As shown in FIG. 2D, portions of the silicon oxide layer 50 are selectively removed using the photoresist layer pattern 60 as a mask, thereby forming a silicon oxide pattern 55. After that, the photoresist pattern 60 is completely removed.
Referring to FIG. 2E, a layer 70 of a conductive material (e.g., a second polysilicon layer) is formed on the first polysilicon layer 40 and the silicon oxide pattern 55 (e.g., by a conformal deposition technique, such as CVD). At this time, the first and second polysilicon layers 40 and 70 are electrically connected to each other in the areas except the silicon oxide pattern 55.
As shown in FIG. 2F, the first and second polysilicon layers 40 and 70 are selectively removed by anisotropic dry etching (e.g., RIE, or Reactive Ion Etching). Accordingly, the second polysilicon layer 70 remains at a sidewall of the silicon oxide pattern 55, and the first polysilicon layer 40 remains below the silicon oxide pattern 55 and the second polysilicon layer 70, thereby forming a cylindrical lower electrode (e.g., a combination of polysilicon structures 40 and 70). At this time, the anisotropic dry etch process is performed by using the nitride layer 30 as an etch stopper.
As shown in FIG. 2G, the silicon oxide pattern 55 is completely removed, leaving the cylindrical capacitor lower electrode. The silicon oxide pattern 55 may be removed by wet etching.
As shown in FIG. 2H, a dielectric layer 80 (e.g., a silicon oxide such as a TEOS-based oxide) is (conformally) deposited on the entire surface of the substrate including the capacitor lower electrode, to form a capacitor dielectric. Then, a conductive capacitor upper electrode material 90 is formed (by blanket deposition, such as sputtering, PVD, evaporation or CVD) on the dielectric layer 80. The upper capacitor is completed by planarizing the conductive material 90 (e.g., by etchback or polishing), and a final photolithography step can be performed to remove conductive material 90 from areas outside the vertical lower capacitor structures 70.
As shown in FIG. 3, DRAM cell 200 may be formed upon a semiconductor substrate 210. In general, substrate 200 may be a silicon substrate and may include transistor diffusion regions 212 and isolation regions 214, as is known in the art. Transistor gate electrodes 220 may be formed on the substrate layer in a normal manner by forming a stack of one or more dielectric and conductive (e.g., polysilicon and optional metal silicide) layers. Next the interlevel dielectric, which nay contain USG layer 230, FSG layer 240, second USG layer 250, TEOS layer 260 and silicon nitride layer 270, may be formed on the conductive layer of gate electrodes 220. Silicon nitride layer 270 is generally patterned as described above to form a bottom plate opening, then layers 230-260 may be patterned to form a via opening, which exposes a conductive layer (generally tungsten contacts to a source/din terminal 212) of gate electrodes 220. After the openings are formed, conductive material 280 (typically, polysilicon) may be deposited on silicon nitride layer 270 and with the opening. By filing the openings with the conductive material, a bottom plate and a conductive plug may be formed, making electrical contact with the underlying conductive layer of gate electrodes 220. After portions of the polysilicon layer are removed from the top surface of silicon nitride layer 270, the upper and lower electrodes of memory cell capacitor 290 are formed in multi-step process, as described in part above. In an alterative to the s described with red to FIG. 2H, a dielectric layer 285 may be blanket deposited on the lower electrode structures 40 and 70 and on nitride layer 30, then planarized and photolithographically patterned to selectively remove the dielectric 285 from within the cylindrical lower electrode 40/70. Then a conformal capacitor dielectric (similar to dielectric 80 if FIG. 2H) and another conductive layer 295 are deposited to form pre-capacitor 290. A capacitor is subsequently formed by planarizing or removing the conductive layer 295 above the upper surface of the capacitor dielectric. (i.e., outside the lower capacitor electrode) as described herein.
However, the method for fabricating the lower electrode of the cylindrical capacitor has the following disadvantages. First, as described above, in order to form the lower electrode of the cylindrical capacitor, photolithography may be performed several times, thereby complicating fabrication process steps, and lowering yield. Also, time and cost for fabrication of the capacitor tend to increase with the number of photolithography and other processing steps. The large number of processing steps may decrease yield by increasing the probability for defects.
Also, in the exemplary related art fabrication process, the silicon oxide layer pattern may be removed by wet etching, whereby the polysilicon layer or lower electrode may be damaged. Also, a wet etchant may penetrate the edge of the wafer, thereby damaging a chip on or near the water edge. Therefore, a need exists for an improved method for forming a cylinder-type memory cell capacitor. By reducing the number of processing steps, the improved method may advantageously decrease processing time and maintaining costs, while increasing yield.